Abstract
Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead. © 2013 EDAA.
| Original language | English |
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| Title of host publication | Proceedings -Design, Automation and Test in Europe, DATE |
| Pages | 1247-1250 |
| Publication status | Published - Mar 2013 |
| Event | 16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013) - Grenoble, France Duration: 18 Mar 2013 → 22 Mar 2013 https://ieeexplore.ieee.org/xpl/conhome/6507370/proceeding |
Publication series
| Name | |
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| ISSN (Print) | 1530-1591 |
Conference
| Conference | 16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013) |
|---|---|
| Place | France |
| City | Grenoble |
| Period | 18/03/13 → 22/03/13 |
| Internet address |
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