Bidirectional multi-level spatial coded exposure CMOS capacitive TIA pixel design

Yi Luo; Shahriar Mirabbasi; Derek Ho

doi:10.1109/EDSSC.2016.7785307

Bidirectional multi-level spatial coded exposure CMOS capacitive TIA pixel design

Yi Luo^*, Shahriar Mirabbasi, Derek Ho

^*Corresponding author for this work

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

1 Citation (Scopus)

Abstract

Over the last decade, computational cameras have demonstrated superior performance in a variety of applications. Currently, optical encoding is implemented using components that are typically not integrated on the image sensor chip. This results in camera systems with large physical sizes, performance compromises, and implementation challenges, particularly in applications where size and power are constrained. In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) pixel structure with bidirectional multi-level spatial coded exposure encoding capability for computational imaging. Based on a capacitive transimpedance amplifier (CTIA) core, the proposed pixel architecture achieves bidirectional multi-level optical encoding, and is compatible with monolithic CMOS implementation. Designed and laid out in a standard 0.13-pm CMOS process, the pixel occupies an area of 13.8 pm × 13.8 pm with a fill factor of 30%.

Original language	English
Title of host publication	2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)
Publisher	IEEE
Pages	460-463
ISBN (Print)	9781509018307
DOIs	https://doi.org/10.1109/EDSSC.2016.7785307
Publication status	Published - 15 Dec 2016
Event	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong, China Duration: 3 Aug 2016 → 5 Aug 2016

Conference

Conference	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
Place	Hong Kong, China
City	Hong Kong
Period	3/08/16 → 5/08/16

Research Keywords

CMOS image sensor
CTIA pixel
multi-level exposure
optical encoding
computational imaging
IMAGE

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10.1109/EDSSC.2016.7785307

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@inproceedings{86be172f4803427b80c8a21a08923aad,

title = "Bidirectional multi-level spatial coded exposure CMOS capacitive TIA pixel design",

abstract = "Over the last decade, computational cameras have demonstrated superior performance in a variety of applications. Currently, optical encoding is implemented using components that are typically not integrated on the image sensor chip. This results in camera systems with large physical sizes, performance compromises, and implementation challenges, particularly in applications where size and power are constrained. In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) pixel structure with bidirectional multi-level spatial coded exposure encoding capability for computational imaging. Based on a capacitive transimpedance amplifier (CTIA) core, the proposed pixel architecture achieves bidirectional multi-level optical encoding, and is compatible with monolithic CMOS implementation. Designed and laid out in a standard 0.13-pm CMOS process, the pixel occupies an area of 13.8 pm × 13.8 pm with a fill factor of 30%.",

keywords = "CMOS image sensor, CTIA pixel, multi-level exposure, optical encoding, computational imaging, IMAGE",

author = "Yi Luo and Shahriar Mirabbasi and Derek Ho",

year = "2016",

month = dec,

day = "15",

doi = "10.1109/EDSSC.2016.7785307",

language = "English",

isbn = "9781509018307",

pages = "460--463",

booktitle = "2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)",

publisher = "IEEE",

address = "United States",

note = "2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 ; Conference date: 03-08-2016 Through 05-08-2016",

}

Luo, Y, Mirabbasi, S & Ho, D 2016, Bidirectional multi-level spatial coded exposure CMOS capacitive TIA pixel design. in 2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)., 7785307, IEEE, pp. 460-463, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016, Hong Kong, Hong Kong, China, 3/08/16. https://doi.org/10.1109/EDSSC.2016.7785307

Bidirectional multi-level spatial coded exposure CMOS capacitive TIA pixel design. / Luo, Yi; Mirabbasi, Shahriar; Ho, Derek.
2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC). IEEE, 2016. p. 460-463 7785307.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - Bidirectional multi-level spatial coded exposure CMOS capacitive TIA pixel design

AU - Luo, Yi

AU - Mirabbasi, Shahriar

AU - Ho, Derek

PY - 2016/12/15

Y1 - 2016/12/15

N2 - Over the last decade, computational cameras have demonstrated superior performance in a variety of applications. Currently, optical encoding is implemented using components that are typically not integrated on the image sensor chip. This results in camera systems with large physical sizes, performance compromises, and implementation challenges, particularly in applications where size and power are constrained. In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) pixel structure with bidirectional multi-level spatial coded exposure encoding capability for computational imaging. Based on a capacitive transimpedance amplifier (CTIA) core, the proposed pixel architecture achieves bidirectional multi-level optical encoding, and is compatible with monolithic CMOS implementation. Designed and laid out in a standard 0.13-pm CMOS process, the pixel occupies an area of 13.8 pm × 13.8 pm with a fill factor of 30%.

AB - Over the last decade, computational cameras have demonstrated superior performance in a variety of applications. Currently, optical encoding is implemented using components that are typically not integrated on the image sensor chip. This results in camera systems with large physical sizes, performance compromises, and implementation challenges, particularly in applications where size and power are constrained. In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) pixel structure with bidirectional multi-level spatial coded exposure encoding capability for computational imaging. Based on a capacitive transimpedance amplifier (CTIA) core, the proposed pixel architecture achieves bidirectional multi-level optical encoding, and is compatible with monolithic CMOS implementation. Designed and laid out in a standard 0.13-pm CMOS process, the pixel occupies an area of 13.8 pm × 13.8 pm with a fill factor of 30%.

KW - CMOS image sensor

KW - CTIA pixel

KW - multi-level exposure

KW - optical encoding

KW - computational imaging

KW - IMAGE

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DO - 10.1109/EDSSC.2016.7785307

M3 - RGC 32 - Refereed conference paper (with host publication)

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BT - 2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)

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Y2 - 3 August 2016 through 5 August 2016

ER -

Bidirectional multi-level spatial coded exposure CMOS capacitive TIA pixel design

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