Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)

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Detail(s)

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019
PublisherIEEE
Pages288-291
ISBN (Electronic)978-1-7281-1601-3
Publication statusPublished - Jul 2019

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2019-July
ISSN (Print)1063-6862

Conference

Title30th IEEE International Conference on
Application-Specific Systems, Architectures and Processors (ASAP 2019)
LocationCornell Tech
PlaceUnited States
Period15 - 17 July 2019

Abstract

Ternary content-addressable memory (CAM) is an associative memory which supports the storing of don’t care (‘X’) bits. Field programmable gate arrays (FPGAs) are enriched with high speed hardware components such as memory elements, logical blocks, but do not have support for a TCAM. Researchers have emulated TCAM inside FPGAs using static random-access memory (SRAM) blocks, flip-flops, and lookup tables (LUTs). Power requirement of these emulated TCAMs is very high due to the parallel comparison of each bit of the search key with the stored words. In this paper, we present a bank-selective strategy to decrease the amount of power consumed by gate-based TCAM on FPGA. Instead of comparing the search key with all of the stored words, our proposed architecture compares the search key with a selected number of stored words based on classifier-bits in search key. A sample of 64×36 is implemented on Xilinx Virtex-6 FPGA with four banks, which reduced the power consumption by 44.8% compared to the state-of-the-art TCAM architecture. Hardware utilization of the proposed TCAM on FPGA with four banks is also reduced by 6% and 8% in the form of slice registers (SRs) and lookup tables (LUTs), respectively.

Research Area(s)

  • Application-specific integrated circuit (ASIC), Field-programmable gate arrays (FPGAs), Software defined network (SDN), Ternary content addressable memory (TCAM)

Citation Format(s)

Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs. / Irfan, Muhammad; Cheung, Ray C. C.; Ullah, Zahid.

Proceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019. IEEE, 2019. p. 288-291 8825147 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2019-July).

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)