Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs

Ternary content-addressable memory (CAM) is an associative memory which supports the storing of don’t care (‘X’) bits. Field programmable gate arrays (FPGAs) are enriched with high speed hardware components such as memory elements, logical blocks, but do not have support for a TCAM. Researchers have emulated TCAM inside FPGAs using static random-access memory (SRAM) blocks, flip-flops, and lookup tables (LUTs). Power requirement of these emulated TCAMs is very high due to the parallel comparison of each bit of the search key with the stored words. In this paper, we present a bank-selective strategy to decrease the amount of power consumed by gate-based TCAM on FPGA. Instead of comparing the search key with all of the stored words, our proposed architecture compares the search key with a selected number of stored words based on classifier-bits in search key. A sample of 64×36 is implemented on Xilinx Virtex-6 FPGA with four banks, which reduced the power consumption by 44.8% compared to the state-of-the-art TCAM architecture. Hardware utilization of the proposed TCAM on FPGA with four banks is also reduced by 6% and 8% in the form of slice registers (SRs) and lookup tables (LUTs), respectively.