Abstract
Ahippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network applicationspecific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)-generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122mm2 and test power of 84.4 μW. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.
| Original language | English |
|---|---|
| Pages (from-to) | 2472-2499 |
| Journal | Neural Computation |
| Volume | 30 |
| Issue number | 9 |
| Online published | 16 Aug 2018 |
| DOIs | |
| Publication status | Published - Sept 2018 |
Research Keywords
- VLSI
- SYSTEM
- IDENTIFICATION
- FACILITATION
- NETWORKS
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