ASIC-based Gauss error function module design for Neural Network application

Zhi-Tong Qiao; Yan Han; Jian Lei; R. C. C. Cheung; Will X. Y. Li; Hiao-Xia Han

doi:10.1109/ICSICT.2016.7998716

ASIC-based Gauss error function module design for Neural Network application

Zhi-Tong Qiao, Yan Han^*, Jian Lei, R. C. C. Cheung, Will X. Y. Li, Hiao-Xia Han

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Abstract

The first ASIC-based Gauss error function (GEF) module is proposed and fabricated in SMIC 180-nm process in this paper. A novel method is proposed to be used in the design. Experimental results show that compared with the design based on Taylor expansion method, the proposed design decreases the absolute error by 99.21%, reduces the area by 77.21% and reduces the delay by 11.96%. It can be used as a Soft Intellectual Property (IP) Core or Digital Signal Processor (DSP) to be easily applied to all kinds of Neural Network applications. The design proposed and the corresponding design and optimization methods can promote the research and development of the implantable neural prosthesis bio-chip and neural network.

Original language	English
Title of host publication	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings
Editors	Yu-Long Jiang, Ting-Ao Tang, Ru Huang
Publisher	IEEE
Pages	1285-1287
ISBN (Electronic)	978-1-4673-9719-3
ISBN (Print)	9781467397179
DOIs	https://doi.org/10.1109/ICSICT.2016.7998716
Publication status	Published - 27 Oct 2016
Event	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016 - Hangzhou, China Duration: 25 Oct 2016 → 28 Oct 2016 http://www.icsict.com/uploadfiles/file/20161008-FinalProgram.pdf

Conference

Conference	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016
Abbreviated title	ICSICT-2016
Place	China
City	Hangzhou
Period	25/10/16 → 28/10/16
Internet address	http://www.icsict.com/uploadfiles/file/20161008-FinalProgram.pdf

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Qiao, Z.-T., Han, Y., Lei, J., Cheung, R. C. C., Li, W. X. Y., & Han, H.-X. (2016). ASIC-based Gauss error function module design for Neural Network application. In Y.-L. Jiang, T.-A. Tang, & R. Huang (Eds.), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings (pp. 1285-1287). Article 7998716 IEEE. https://doi.org/10.1109/ICSICT.2016.7998716

@inproceedings{994d6790f5294998a4bc42186ed47311,

title = "ASIC-based Gauss error function module design for Neural Network application",

abstract = "The first ASIC-based Gauss error function (GEF) module is proposed and fabricated in SMIC 180-nm process in this paper. A novel method is proposed to be used in the design. Experimental results show that compared with the design based on Taylor expansion method, the proposed design decreases the absolute error by 99.21%, reduces the area by 77.21% and reduces the delay by 11.96%. It can be used as a Soft Intellectual Property (IP) Core or Digital Signal Processor (DSP) to be easily applied to all kinds of Neural Network applications. The design proposed and the corresponding design and optimization methods can promote the research and development of the implantable neural prosthesis bio-chip and neural network.",

author = "Zhi-Tong Qiao and Yan Han and Jian Lei and Cheung, {R. C. C.} and Li, {Will X. Y.} and Hiao-Xia Han",

year = "2016",

month = oct,

day = "27",

doi = "10.1109/ICSICT.2016.7998716",

language = "English",

isbn = "9781467397179",

pages = "1285--1287",

editor = "Yu-Long Jiang and Ting-Ao Tang and Ru Huang",

booktitle = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings",

publisher = "IEEE",

address = "United States",

note = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016, ICSICT-2016 ; Conference date: 25-10-2016 Through 28-10-2016",

url = "http://www.icsict.com/uploadfiles/file/20161008-FinalProgram.pdf",

}

Qiao, Z-T, Han, Y, Lei, J, Cheung, RCC, Li, WXY & Han, H-X 2016, ASIC-based Gauss error function module design for Neural Network application. in Y-L Jiang, T-A Tang & R Huang (eds), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings., 7998716, IEEE, pp. 1285-1287, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016, Hangzhou, China, 25/10/16. https://doi.org/10.1109/ICSICT.2016.7998716

ASIC-based Gauss error function module design for Neural Network application. / Qiao, Zhi-Tong; Han, Yan; Lei, Jian et al.
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings. ed. / Yu-Long Jiang; Ting-Ao Tang; Ru Huang. IEEE, 2016. p. 1285-1287 7998716.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - ASIC-based Gauss error function module design for Neural Network application

AU - Qiao, Zhi-Tong

AU - Han, Yan

AU - Lei, Jian

AU - Cheung, R. C. C.

AU - Li, Will X. Y.

AU - Han, Hiao-Xia

PY - 2016/10/27

Y1 - 2016/10/27

N2 - The first ASIC-based Gauss error function (GEF) module is proposed and fabricated in SMIC 180-nm process in this paper. A novel method is proposed to be used in the design. Experimental results show that compared with the design based on Taylor expansion method, the proposed design decreases the absolute error by 99.21%, reduces the area by 77.21% and reduces the delay by 11.96%. It can be used as a Soft Intellectual Property (IP) Core or Digital Signal Processor (DSP) to be easily applied to all kinds of Neural Network applications. The design proposed and the corresponding design and optimization methods can promote the research and development of the implantable neural prosthesis bio-chip and neural network.

AB - The first ASIC-based Gauss error function (GEF) module is proposed and fabricated in SMIC 180-nm process in this paper. A novel method is proposed to be used in the design. Experimental results show that compared with the design based on Taylor expansion method, the proposed design decreases the absolute error by 99.21%, reduces the area by 77.21% and reduces the delay by 11.96%. It can be used as a Soft Intellectual Property (IP) Core or Digital Signal Processor (DSP) to be easily applied to all kinds of Neural Network applications. The design proposed and the corresponding design and optimization methods can promote the research and development of the implantable neural prosthesis bio-chip and neural network.

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DO - 10.1109/ICSICT.2016.7998716

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9781467397179

SP - 1285

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BT - 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings

A2 - Jiang, Yu-Long

A2 - Tang, Ting-Ao

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PB - IEEE

T2 - 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016

Y2 - 25 October 2016 through 28 October 2016

ER -

ASIC-based Gauss error function module design for Neural Network application

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