Abstract
With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.
| Original language | English |
|---|---|
| Article number | 7527690 |
| Pages (from-to) | 488-501 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 25 |
| Issue number | 2 |
| Online published | 1 Aug 2016 |
| DOIs | |
| Publication status | Published - Feb 2017 |
| Externally published | Yes |
Research Keywords
- Antiwear leveling
- Bose-Chaudhuri-Hocquenghem (BCH)
- Flash memory
- Flash storage device
- hybrid error correction code (ECC)
- low-density parity check (LDPC)
- solid-state drive (SSD)
- Storage systems
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