Skip to main navigation Skip to search Skip to main content

Antiwear Leveling Design for SSDs With Hybrid ECC Capability

  • Chien-Chung Ho
  • , Yu-Ping Liu
  • , Yuan-Hao Chang
  • , Tei-Wei Kuo

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

Abstract

With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.
Original languageEnglish
Article number7527690
Pages (from-to)488-501
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number2
Online published1 Aug 2016
DOIs
Publication statusPublished - Feb 2017
Externally publishedYes

Research Keywords

  • Antiwear leveling
  • Bose-Chaudhuri-Hocquenghem (BCH)
  • Flash memory
  • Flash storage device
  • hybrid error correction code (ECC)
  • low-density parity check (LDPC)
  • solid-state drive (SSD)
  • Storage systems

Fingerprint

Dive into the research topics of 'Antiwear Leveling Design for SSDs With Hybrid ECC Capability'. Together they form a unique fingerprint.

Cite this