Antiwear Leveling Design for SSDs With Hybrid ECC Capability

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

9 Scopus Citations
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Author(s)

Detail(s)

Original languageEnglish
Article number7527690
Pages (from-to)488-501
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number2
Online published1 Aug 2016
Publication statusPublished - Feb 2017
Externally publishedYes

Abstract

With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.

Research Area(s)

  • Antiwear leveling, Bose-Chaudhuri-Hocquenghem (BCH), Flash memory, Flash storage device, hybrid error correction code (ECC), low-density parity check (LDPC), solid-state drive (SSD), Storage systems

Citation Format(s)

Antiwear Leveling Design for SSDs With Hybrid ECC Capability. / Ho, Chien-Chung; Liu, Yu-Ping; Chang, Yuan-Hao; Kuo, Tei-Wei.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 2, 7527690, 02.2017, p. 488-501.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review