Analytical gate fringe capacitance model for nanoscale MOSFET with layout dependent effect and process variations

In this paper, we present an analytical closed model for the gate to source/drain fringing capacitance (C_f) of nanoscale metal oxide semiconductor field effect transistors (MOSFETs), with the consideration of layout dependent effects and process fluctuations. A kind of field-poly structure on shallow trench isolation (STI) is used to separate C_f from other gate-around parasitic capacitances. A significant layout-dependent-effect is found in C_f for the case with high contact density. Based on the device structure, C_f is divided and analytically modeled by three dual-k perpendicular-plate capacitances. The effects of gate to contact space (CPS), contact to contact space (CCS) and the process variations, such as the over-etching of source/drain contact, are taken into account. The proposed model is validated on 40 nm MOSFETs, with a series of layout parameters, and good agreement is obtained between the modeled and measured data over a large range of CPS and CCS. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.