An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review

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Author(s)

  • Shun Yan
  • Zhengyan Liu
  • Yun Wang
  • Chenglong Zeng
  • Qiang Liu
  • Bowen Cheng

Related Research Unit(s)

Detail(s)

Original languageEnglish
Title of host publication2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021
Subtitle of host publicationProceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17-23
ISBN (Electronic)978-1-6654-3759-2
ISBN (Print)978-1-6654-4243-5
Publication statusPublished - 2021

Publication series

NameInternational Conference on Field Programmable Logic and Applications
ISSN (Print)1946-147X
ISSN (Electronic)1946-1488

Conference

Title31st International Conference on Field-Programmable Logic and Applications (FPL 2021)
LocationVirtual
PlaceGermany
CityDresden
Period30 August - 3 September 2021

Abstract

Convolutional neural networks (CNNs) have been widely deployed in computer vision tasks. However, the computation and resource intensive characteristics of CNN bring obstacles to its application on embedded systems. MobileNet, as a representative of compact models, can reduce the amount of parameters and computation. A high-performance inference accelerator on FPGA for MobileNet is proposed in this paper. With respect to the three types of convolution operations, multiple parallel strategies are exploited and the corresponding hardware structures such as input buffer and configurable adder tree are designed. With respect to the bottleneck block, a dedicated architecture is proposed to reduce data transmission time. In addition, a hardware padding scheme to improve the efficiency of padding is proposed. The accelerator implemented on Virtex-7 FPGA reaches 70.8% Top -1 accuracy under 8 -bit quantization. The accelerator achieves 302.3 FPS and 181.8 GOPS, which obtains 22.7x, 3.9x and 1.4x speedup compared to the implementations in Snapdragon 821 CPU, i7-6700HQ CPU and GTX 960M GPU, respectively.

Citation Format(s)

An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics. / Yan, Shun; Liu, Zhengyan; Wang, Yun; Zeng, Chenglong; Liu, Qiang; Cheng, Bowen; Cheung, Ray C.C.

2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021: Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. p. 17-23 (International Conference on Field Programmable Logic and Applications).

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review