An FPGA-based acceleration platform for auction algorithm

Pengfei Zhu; Chun Zhang; Hua Li; Ray C.C. Cheung; Bryan Hu

doi:10.1109/ISCAS.2012.6271395

An FPGA-based acceleration platform for auction algorithm

Pengfei Zhu
, Chun Zhang
, Hua Li
, Ray C.C. Cheung
, Bryan Hu

Department of Electrical Engineering

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

8 Citations (Scopus)

Abstract

Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for FPGA hardware implementation. In this paper, we focus on the acceleration of auction algorithm to solve assignment problem. The main contribution is to set up a flexible platform to generate efficient and extendable application-based hardware acceleration. It aims at solving both symmetric and asymmetric assignment problem. Experimental results show that 10X speedup can be achieved using 128 Processing Elements for the problem size of 500. © 2012 IEEE.

Original language	English
Title of host publication	ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
Pages	1002-1005
DOIs	https://doi.org/10.1109/ISCAS.2012.6271395
Publication status	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012) - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012)
Abbreviated title	ISCAS 2012
Place	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271395

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title = "An FPGA-based acceleration platform for auction algorithm",

abstract = "Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for FPGA hardware implementation. In this paper, we focus on the acceleration of auction algorithm to solve assignment problem. The main contribution is to set up a flexible platform to generate efficient and extendable application-based hardware acceleration. It aims at solving both symmetric and asymmetric assignment problem. Experimental results show that 10X speedup can be achieved using 128 Processing Elements for the problem size of 500. {\textcopyright} 2012 IEEE.",

author = "Pengfei Zhu and Chun Zhang and Hua Li and Cheung, \{Ray C.C.\} and Bryan Hu",

year = "2012",

doi = "10.1109/ISCAS.2012.6271395",

language = "English",

pages = "1002--1005",

booktitle = "ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems",

note = "2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012), ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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TY - GEN

T1 - An FPGA-based acceleration platform for auction algorithm

AU - Zhu, Pengfei

AU - Zhang, Chun

AU - Li, Hua

AU - Cheung, Ray C.C.

AU - Hu, Bryan

PY - 2012

Y1 - 2012

N2 - Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for FPGA hardware implementation. In this paper, we focus on the acceleration of auction algorithm to solve assignment problem. The main contribution is to set up a flexible platform to generate efficient and extendable application-based hardware acceleration. It aims at solving both symmetric and asymmetric assignment problem. Experimental results show that 10X speedup can be achieved using 128 Processing Elements for the problem size of 500. © 2012 IEEE.

AB - Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for FPGA hardware implementation. In this paper, we focus on the acceleration of auction algorithm to solve assignment problem. The main contribution is to set up a flexible platform to generate efficient and extendable application-based hardware acceleration. It aims at solving both symmetric and asymmetric assignment problem. Experimental results show that 10X speedup can be achieved using 128 Processing Elements for the problem size of 500. © 2012 IEEE.

UR - https://www.scopus.com/pages/publications/84866600459

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84866600459&origin=recordpage

U2 - 10.1109/ISCAS.2012.6271395

DO - 10.1109/ISCAS.2012.6271395

M3 - RGC 32 - Refereed conference paper (with host publication)

SP - 1002

EP - 1005

BT - ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

T2 - 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012)

Y2 - 20 May 2012 through 23 May 2012

ER -

An FPGA-based acceleration platform for auction algorithm

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