An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop
Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45) › 32_Refereed conference paper (with ISBN/ISSN) › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Title of host publication | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
| Pages | 325-328 |
| Publication status | Published - Dec 2007 |
Conference
| Title | IEEE Conference on Electron Devices and Solid-State Circuits 2007 (EDSSC 2007) |
|---|---|
| Place | Taiwan |
| City | Tainan |
| Period | 20 - 22 December 2007 |
Link(s)
Abstract
This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed I)FF consists of a dynamic master and a half-static slave built with a pass-transistor clockgating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 μm mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.
Citation Format(s)
An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop. / Tam, Wing-Shan; Wong, Oi-Ying; Mok, Ka-Yan et al.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 325-328 4450128.Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45) › 32_Refereed conference paper (with ISBN/ISSN) › peer-review
