An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop

Wing-Shan Tam; Oi-Ying Wong; Ka-Yan Mok; Chi-Wah Kok; Hei Wong

doi:10.1109/EDSSC.2007.4450128

An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop

Wing-Shan Tam
, Oi-Ying Wong
, Ka-Yan Mok
, Chi-Wah Kok
, Hei Wong^*

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

1 Citation (Scopus)

Abstract

This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed I)FF consists of a dynamic master and a half-static slave built with a pass-transistor clockgating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 μm mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	325-328
DOIs	https://doi.org/10.1109/EDSSC.2007.4450128
Publication status	Published - Dec 2007
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007 (EDSSC 2007) - Tainan, Taiwan, China Duration: 20 Dec 2007 → 22 Dec 2007

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits 2007 (EDSSC 2007)
Place	Taiwan, China
City	Tainan
Period	20/12/07 → 22/12/07

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This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/EDSSC.2007.4450128

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@inproceedings{3211b425446a4777a0a61600743ee952,

title = "An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop",

abstract = "This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed I)FF consists of a dynamic master and a half-static slave built with a pass-transistor clockgating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 μm mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.",

author = "Wing-Shan Tam and Oi-Ying Wong and Ka-Yan Mok and Chi-Wah Kok and Hei Wong",

year = "2007",

month = dec,

doi = "10.1109/EDSSC.2007.4450128",

language = "English",

isbn = "1424406374",

pages = "325--328",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007 (EDSSC 2007) ; Conference date: 20-12-2007 Through 22-12-2007",

}

Tam, W-S, Wong, O-Y, Mok, K-Y, Kok, C-W & Wong, H 2007, An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop. in IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450128, pp. 325-328, IEEE Conference on Electron Devices and Solid-State Circuits 2007 (EDSSC 2007), Tainan, Taiwan, China, 20/12/07. https://doi.org/10.1109/EDSSC.2007.4450128

An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop. / Tam, Wing-Shan; Wong, Oi-Ying; Mok, Ka-Yan et al.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 325-328 4450128.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop

AU - Tam, Wing-Shan

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AU - Mok, Ka-Yan

AU - Kok, Chi-Wah

AU - Wong, Hei

PY - 2007/12

Y1 - 2007/12

N2 - This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed I)FF consists of a dynamic master and a half-static slave built with a pass-transistor clockgating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 μm mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.

AB - This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed I)FF consists of a dynamic master and a half-static slave built with a pass-transistor clockgating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 μm mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.

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U2 - 10.1109/EDSSC.2007.4450128

DO - 10.1109/EDSSC.2007.4450128

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 1424406374

SN - 9781424406371

SP - 325

EP - 328

BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007 (EDSSC 2007)

Y2 - 20 December 2007 through 22 December 2007

ER -

An Energy Efficient Half-Static Clock-Gating D-type Flip-Flop

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