Abstract
This paper presents a new design of half-static clock-gating D-type flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock-gating circuitry. The new circuit has a very compact size, and can achieve low-power dissipation, especially in the case of low data activity. SPICE simulation results of the proposed DFF implemented with 0.18 μm CMOS technology are presented, which shows that the overall performance of the present design is better than most of the DFFs reported in literatures.
| Original language | English |
|---|---|
| Pages (from-to) | 635-654 |
| Journal | Journal of Circuits, Systems and Computers |
| Volume | 19 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - May 2010 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy -
SDG 9 Industry, Innovation, and Infrastructure
Research Keywords
- D flip-flop
- Flip-flop
- Half-static flip-flop
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