An ASIC Design of a High-Speed Clock and Data Recovery Circuit

Chi Wai  Ng; Kai Hung Yu; Chiu Wing Sham; Chi Kong Tse

An ASIC Design of a High-Speed Clock and Data Recovery Circuit

Chi Wai Ng, Kai Hung Yu, Chiu Wing Sham, Chi Kong Tse

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Original language	English
Title of host publication	International Conference on Electronics and Information Engineering (ICEIE' 2011)
Pages	1-6
Publication status	Published - Sept 2011
Externally published	Yes
Event	2011 2nd International Conference on Electronics and Information Engineering - 天津理工大学, Tianjin, China Duration: 9 Sept 2011 → 11 Sept 2011 http://www.haozhanhui.com/meeting/311.html

Conference

Conference	2011 2nd International Conference on Electronics and Information Engineering
Country/Territory	China
City	Tianjin
Period	9/09/11 → 11/09/11
Internet address	http://www.haozhanhui.com/meeting/311.html

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@inproceedings{71c2d7d0325f49f184d193bb9d545288,

title = "An ASIC Design of a High-Speed Clock and Data Recovery Circuit",

author = "Ng, {Chi Wai} and Yu, {Kai Hung} and Sham, {Chiu Wing} and Tse, {Chi Kong}",

note = "Publication information for this record has been verified with the author(s) concerned.; 2011 2nd International Conference on Electronics and Information Engineering ; Conference date: 09-09-2011 Through 11-09-2011",

year = "2011",

month = sep,

language = "English",

pages = "1--6",

booktitle = "International Conference on Electronics and Information Engineering (ICEIE' 2011)",

url = "http://www.haozhanhui.com/meeting/311.html",

}

TY - GEN

T1 - An ASIC Design of a High-Speed Clock and Data Recovery Circuit

AU - Ng, Chi Wai

AU - Yu, Kai Hung

AU - Sham, Chiu Wing

AU - Tse, Chi Kong

N1 - Publication information for this record has been verified with the author(s) concerned.

PY - 2011/9

Y1 - 2011/9

UR - http://ira.lib.polyu.edu.hk/handle/10397/50808

M3 - RGC 32 - Refereed conference paper (with host publication)

SP - 1

EP - 6

BT - International Conference on Electronics and Information Engineering (ICEIE' 2011)

T2 - 2011 2nd International Conference on Electronics and Information Engineering

Y2 - 9 September 2011 through 11 September 2011

ER -

An ASIC Design of a High-Speed Clock and Data Recovery Circuit

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