An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor

Keni Qiu; Yuanhui Ni; Weigong Zhang; Jing Wang; Xiaoqiang Wu; Chun Jason Xue; Tao Li

doi:10.1109/ICCD.2016.7753255

An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor

Keni Qiu^*, Yuanhui Ni, Weigong Zhang, Jing Wang, Xiaoqiang Wu, Chun Jason Xue, Tao Li

^*Corresponding author for this work

City University of Hong Kong

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

1 Citation (Scopus)

Abstract

Mesh Network-on-Chip (NoC) is a key fabric to interconnect many cores with desirable scalability, reliability and interoperability. We observe that DMA-based bulk data block transfer exhibits non-negligible NoC latency due to heavy congestions. Loop tiling is an effective way to partition data space for SPM+DMA-based data block transfer. Nevertheless, we observe that the unbalanced NoC latency can degrade the effectiveness of loop tiling in a uniform fashion. In this paper, we propose a NoC-aware Non-Uniform Loop Tiling (NULT) scheme to improve DMA performance. A NULT framework is built on the proposed model to adaptively hide DMA latency into computation time and reduce the overall execution time. The framework first groups cores into different families taking into account their distance-to-data in NoC. Then a heuristic method is presented to solve the near optimal tiling factors for each core family. In this way, different core families are assigned non-uniform tiling sizes. We evaluate the NULT scheme on the NIRGAM platform. Compared to the traditional uniform tiling approach, the proposed NULT technique shows more benefit to overlap memory access time and computation time and thus reduce the overall execution time of a loop nest.

Original language	English
Title of host publication	Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
Publisher	IEEE
Pages	9-16
ISBN (Print)	9781509051427
DOIs	https://doi.org/10.1109/ICCD.2016.7753255
Publication status	Published - 22 Nov 2016
Event	34th IEEE International Conference on Computer Design, ICCD 2016 - Scottsdale, United States Duration: 2 Oct 2016 → 5 Oct 2016

Publication series

Name	Proceedings IEEE International Conference on Computer Design
Publisher	IEEE
ISSN (Print)	1063-6404

Conference

Conference	34th IEEE International Conference on Computer Design, ICCD 2016
Place	United States
City	Scottsdale
Period	2/10/16 → 5/10/16

Funding

This work is supported by Beijing Advanced Innovation Center for Imaging Technology, Guangdong Innovative Research Team Program [Project No. 201001D0104726115], PhD Start-up Fund of Natural Science Foundation of Guangdong Province, China [Project No. 2014A030310344], the Project of Construction of Innovative Teams and Teacher Career Development for Universities and Colleges Under Beijing Municipality [Project No. IDHT20150507], National Natural Science Foundation of China [Project No. 61472260, 61402302 and 61502321]. Weigong Zhang is the corresponding author.

Research Keywords

DMA
looping tiling
many-core system
cost model
non-uniform
ARCHITECTURE

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10.1109/ICCD.2016.7753255

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Qiu, K., Ni, Y., Zhang, W., Wang, J., Wu, X., Xue, C. J., & Li, T. (2016). An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor. In Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016 (pp. 9-16). Article 7753255 (Proceedings IEEE International Conference on Computer Design). IEEE. https://doi.org/10.1109/ICCD.2016.7753255

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title = "An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor",

abstract = "Mesh Network-on-Chip (NoC) is a key fabric to interconnect many cores with desirable scalability, reliability and interoperability. We observe that DMA-based bulk data block transfer exhibits non-negligible NoC latency due to heavy congestions. Loop tiling is an effective way to partition data space for SPM+DMA-based data block transfer. Nevertheless, we observe that the unbalanced NoC latency can degrade the effectiveness of loop tiling in a uniform fashion. In this paper, we propose a NoC-aware Non-Uniform Loop Tiling (NULT) scheme to improve DMA performance. A NULT framework is built on the proposed model to adaptively hide DMA latency into computation time and reduce the overall execution time. The framework first groups cores into different families taking into account their distance-to-data in NoC. Then a heuristic method is presented to solve the near optimal tiling factors for each core family. In this way, different core families are assigned non-uniform tiling sizes. We evaluate the NULT scheme on the NIRGAM platform. Compared to the traditional uniform tiling approach, the proposed NULT technique shows more benefit to overlap memory access time and computation time and thus reduce the overall execution time of a loop nest.",

keywords = "DMA, looping tiling, many-core system, cost model, non-uniform, ARCHITECTURE",

author = "Keni Qiu and Yuanhui Ni and Weigong Zhang and Jing Wang and Xiaoqiang Wu and Xue, {Chun Jason} and Tao Li",

year = "2016",

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note = "34th IEEE International Conference on Computer Design, ICCD 2016 ; Conference date: 02-10-2016 Through 05-10-2016",

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Qiu, K, Ni, Y, Zhang, W, Wang, J, Wu, X, Xue, CJ & Li, T 2016, An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor. in Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016., 7753255, Proceedings IEEE International Conference on Computer Design, IEEE, pp. 9-16, 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, United States, 2/10/16. https://doi.org/10.1109/ICCD.2016.7753255

An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor. / Qiu, Keni; Ni, Yuanhui; Zhang, Weigong et al.
Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. IEEE, 2016. p. 9-16 7753255 (Proceedings IEEE International Conference on Computer Design).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor

AU - Qiu, Keni

AU - Ni, Yuanhui

AU - Zhang, Weigong

AU - Wang, Jing

AU - Wu, Xiaoqiang

AU - Xue, Chun Jason

AU - Li, Tao

PY - 2016/11/22

Y1 - 2016/11/22

N2 - Mesh Network-on-Chip (NoC) is a key fabric to interconnect many cores with desirable scalability, reliability and interoperability. We observe that DMA-based bulk data block transfer exhibits non-negligible NoC latency due to heavy congestions. Loop tiling is an effective way to partition data space for SPM+DMA-based data block transfer. Nevertheless, we observe that the unbalanced NoC latency can degrade the effectiveness of loop tiling in a uniform fashion. In this paper, we propose a NoC-aware Non-Uniform Loop Tiling (NULT) scheme to improve DMA performance. A NULT framework is built on the proposed model to adaptively hide DMA latency into computation time and reduce the overall execution time. The framework first groups cores into different families taking into account their distance-to-data in NoC. Then a heuristic method is presented to solve the near optimal tiling factors for each core family. In this way, different core families are assigned non-uniform tiling sizes. We evaluate the NULT scheme on the NIRGAM platform. Compared to the traditional uniform tiling approach, the proposed NULT technique shows more benefit to overlap memory access time and computation time and thus reduce the overall execution time of a loop nest.

AB - Mesh Network-on-Chip (NoC) is a key fabric to interconnect many cores with desirable scalability, reliability and interoperability. We observe that DMA-based bulk data block transfer exhibits non-negligible NoC latency due to heavy congestions. Loop tiling is an effective way to partition data space for SPM+DMA-based data block transfer. Nevertheless, we observe that the unbalanced NoC latency can degrade the effectiveness of loop tiling in a uniform fashion. In this paper, we propose a NoC-aware Non-Uniform Loop Tiling (NULT) scheme to improve DMA performance. A NULT framework is built on the proposed model to adaptively hide DMA latency into computation time and reduce the overall execution time. The framework first groups cores into different families taking into account their distance-to-data in NoC. Then a heuristic method is presented to solve the near optimal tiling factors for each core family. In this way, different core families are assigned non-uniform tiling sizes. We evaluate the NULT scheme on the NIRGAM platform. Compared to the traditional uniform tiling approach, the proposed NULT technique shows more benefit to overlap memory access time and computation time and thus reduce the overall execution time of a loop nest.

KW - DMA

KW - looping tiling

KW - many-core system

KW - cost model

KW - non-uniform

KW - ARCHITECTURE

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BT - Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016

PB - IEEE

T2 - 34th IEEE International Conference on Computer Design, ICCD 2016

Y2 - 2 October 2016 through 5 October 2016

ER -

An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor

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