Address Assignment Sensitive Variable Partitioning and scheduling for DSPS with multiple memory banks

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Fingerprint

???publication_fingerprints_help???

Computer Science

100
Partitioning Computer Science
100
Memory Multiple Computer Science
40
Design Computer Science
20
Model Computer Science
20
Experimental Result Computer Science
20
Parallelism Computer Science
20
Scheduling Algorith... Computer Science
20
Memory Access Computer Science
20
Program Variable Computer Science
20
Arithmetic Instruct... Computer Science
20
Memory Architecture Computer Science
20
Data Memory Computer Science
20
Memory Bandwidth Computer Science
20
Datapath Computer Science
20
Procedure Computer Science
20
Compiler Computer Science

Keyphrases

100
Address Assignment Keyphrases
100
Memory Bank Keyphrases
100
Variable Partitioni... Keyphrases
100
Multiple Memories Keyphrases
80
Address Generation Keyphrases
40
Memory Address Keyphrases
20
Parallelization Keyphrases
20
High Performance Keyphrases
20
Scheduling Algorith... Keyphrases
20
Multiple Data Keyphrases
20
Graph Model Keyphrases
20
Memory Access Keyphrases
20
Data Memory Keyphrases
20
DSP Processor Keyphrases
20
Memory Layout Keyphrases
20
Assignment Reductio... Keyphrases
20
DSP Architecture Keyphrases
20
Memory Architecture Keyphrases
20
Architectural Featu... Keyphrases
20
Memory Bandwidth Keyphrases
20
Efficient Schedulin... Keyphrases
20
Compiler Design Keyphrases
20
Serialism Keyphrases
20
Program Variables Keyphrases

INIS

100
assignments INIS
100
banks INIS
80
units INIS
40
design INIS
40
architecture INIS
20
algorithms INIS
20
performance INIS
20
data INIS
20
capture INIS
20
demand INIS
20
optimization INIS
20
graphs INIS
Research OutputsResearch Output authored by Address Assignment Sensitive Variable Partitioning and scheduling for DSPS with multiple memory banks is tagged with the concept