Adaptively Biased 60-GHz Doherty Power Amplifier in 65-nm CMOS

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalNot applicablepeer-review

4 Scopus Citations
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Author(s)

  • Shichang Chen
  • Gaofeng Wang
  • Zhiqun Cheng
  • Pei Qin
  • Quan Xue

Detail(s)

Original languageEnglish
Article number7865996
Pages (from-to)296-298
Journal / PublicationIEEE Microwave and Wireless Components Letters
Volume27
Issue number3
Publication statusPublished - 1 Mar 2017

Abstract

A 60-GHz Doherty power amplifier (PA) implemented in 65-nm bulk CMOS process is proposed. A novel adaptive biasing network is devised to dynamically adjust the bias voltage of the peaking PA, counteracting its low transconductance caused by the class-C biasing condition. At 60 GHz, the fabricated Doherty PA achieves 22% drain efficiency with a saturation power of 13.2 dBm. The measured results show that over 17% and 8% efficiencies at peak and 6-dB back-off power regions are achieved, respectively, from 57 to 64 GHz.

Research Area(s)

  • Adaptive biasing, cascode, Doherty power amplifier (PA), millimeter-wave (mm-wave) CMOS, power-added efficiency

Citation Format(s)

Adaptively Biased 60-GHz Doherty Power Amplifier in 65-nm CMOS. / Chen, Shichang; Wang, Gaofeng; Cheng, Zhiqun; Qin, Pei; Xue, Quan.

In: IEEE Microwave and Wireless Components Letters, Vol. 27, No. 3, 7865996, 01.03.2017, p. 296-298.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalNot applicablepeer-review