Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
Original language | English |
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Article number | 9106401 |
Pages (from-to) | 37-40 |
Journal / Publication | IEEE Embedded Systems Letters |
Volume | 13 |
Issue number | 2 |
Online published | 2 Jun 2020 |
Publication status | Published - Jun 2021 |
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Abstract
Field-programmable gate array (FPGA)-based ternary content-addressable memories (TCAMs) are constantly evolving in terms of hardware, power consumption, and speed. One disadvantage of these emulated TCAMs is its poor update-latency. Traditional FPGA-based TCAMs have an update-latency of N clock cycles compared to the lookup-latency of one clock cycle, where N is the depth of TCAM. Later, the update-latency is improved to t clock cycles, where t is the number of don’t care bits. In this letter, we presented two mechanisms for updating FPGA-based TCAM and successfully implemented on Xilinx Virtex-6 FPGA: an accelerated MUX-Update mechanism and a cost-effective LUT-Update mechanism. MUX-Update provides an update-latency of W + 1 clock cycles by using only three Input/Output (I/O) pins, whereas W is the width of TCAM. LUT-Update yields a constant update-latency of 2 clock cycles, independent of the size of TCAM, by using W I/O pins.
Research Area(s)
- Field-programmable gate array, ternary content-addressable memory, update-latency, logic gate
Citation Format(s)
Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory. / Irfan, Muhammad; Ullah, Zahid; Sanka, Abdurrashid I.; CHEUNG, Ray C. C.
In: IEEE Embedded Systems Letters, Vol. 13, No. 2, 9106401, 06.2021, p. 37-40.Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review