A V-band 40 nm CMOS phase locked loop with mutual injection locking technique

Qian Zhou; Yan Han; Shifeng Zhang; Xiaoxia Han; Lu Jie; Ray C. C. Cheung; Guangtao Feng

doi:10.1109/ICSICT.2016.7998972

A V-band 40 nm CMOS phase locked loop with mutual injection locking technique

Qian Zhou
, Yan Han
, Shifeng Zhang^*
, Xiaoxia Han
, Lu Jie
, Ray C. C. Cheung
, Guangtao Feng

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Abstract

This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm². The silicon results demonstrate an excellent in-band phase noise of -90 dBc/Hz at 500 kHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz.

Original language	English
Title of host publication	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings
Editors	Yu-Long Jiang, Ting-Ao Tang, Ru Huang
Publisher	IEEE
Pages	539-541
ISBN (Electronic)	978-1-4673-9719-3
ISBN (Print)	9781467397179
DOIs	https://doi.org/10.1109/ICSICT.2016.7998972
Publication status	Published - 27 Oct 2016
Event	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016 - Hangzhou, China Duration: 25 Oct 2016 → 28 Oct 2016 http://www.icsict.com/uploadfiles/file/20161008-FinalProgram.pdf

Conference

Conference	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016
Abbreviated title	ICSICT-2016
Place	China
City	Hangzhou
Period	25/10/16 → 28/10/16
Internet address	http://www.icsict.com/uploadfiles/file/20161008-FinalProgram.pdf

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Zhou, Q., Han, Y., Zhang, S., Han, X., Jie, L., Cheung, R. C. C., & Feng, G. (2016). A V-band 40 nm CMOS phase locked loop with mutual injection locking technique. In Y.-L. Jiang, T.-A. Tang, & R. Huang (Eds.), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings (pp. 539-541). Article 7998972 IEEE. https://doi.org/10.1109/ICSICT.2016.7998972

@inproceedings{a490aba693884db39fc84d0785be1d9d,

title = "A V-band 40 nm CMOS phase locked loop with mutual injection locking technique",

abstract = "This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an excellent in-band phase noise of -90 dBc/Hz at 500 kHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz.",

author = "Qian Zhou and Yan Han and Shifeng Zhang and Xiaoxia Han and Lu Jie and Cheung, \{Ray C. C.\} and Guangtao Feng",

year = "2016",

month = oct,

day = "27",

doi = "10.1109/ICSICT.2016.7998972",

language = "English",

isbn = "9781467397179",

pages = "539--541",

editor = "Yu-Long Jiang and Ting-Ao Tang and Ru Huang",

booktitle = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings",

publisher = "IEEE",

address = "United States",

note = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016, ICSICT-2016 ; Conference date: 25-10-2016 Through 28-10-2016",

url = "http://www.icsict.com/uploadfiles/file/20161008-FinalProgram.pdf",

}

Zhou, Q, Han, Y, Zhang, S, Han, X, Jie, L, Cheung, RCC & Feng, G 2016, A V-band 40 nm CMOS phase locked loop with mutual injection locking technique. in Y-L Jiang, T-A Tang & R Huang (eds), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings., 7998972, IEEE, pp. 539-541, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016, Hangzhou, China, 25/10/16. https://doi.org/10.1109/ICSICT.2016.7998972

A V-band 40 nm CMOS phase locked loop with mutual injection locking technique. / Zhou, Qian; Han, Yan; Zhang, Shifeng et al.
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings. ed. / Yu-Long Jiang; Ting-Ao Tang; Ru Huang. IEEE, 2016. p. 539-541 7998972.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - A V-band 40 nm CMOS phase locked loop with mutual injection locking technique

AU - Zhou, Qian

AU - Han, Yan

AU - Zhang, Shifeng

AU - Han, Xiaoxia

AU - Jie, Lu

AU - Cheung, Ray C. C.

AU - Feng, Guangtao

PY - 2016/10/27

Y1 - 2016/10/27

N2 - This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an excellent in-band phase noise of -90 dBc/Hz at 500 kHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz.

AB - This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an excellent in-band phase noise of -90 dBc/Hz at 500 kHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz.

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UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-85028670638&origin=recordpage

U2 - 10.1109/ICSICT.2016.7998972

DO - 10.1109/ICSICT.2016.7998972

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9781467397179

SP - 539

EP - 541

BT - 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) : Proceedings

A2 - Jiang, Yu-Long

A2 - Tang, Ting-Ao

A2 - Huang, Ru

PB - IEEE

T2 - 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT-2016

Y2 - 25 October 2016 through 28 October 2016

ER -

A V-band 40 nm CMOS phase locked loop with mutual injection locking technique

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