A unified write buffer cache management scheme for flash memory

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

9 Scopus Citations
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Author(s)

  • Liang Shi
  • Jianhua Li
  • Qingan Li
  • Chengmo Yang
  • Xuehai Zhou

Related Research Unit(s)

Detail(s)

Original languageEnglish
Article number6705640
Pages (from-to)2779-2792
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number12
Publication statusPublished - Dec 2014

Abstract

NAND flash memory has been widely adopted in embedded systems as secondary storage. However, the further development of flash memory strongly hinges on the tackling of its inherent implausible characteristics, including read-and-write speed asymmetry, inability of in-place updates, and performance-harmful erase operations. While write buffer cache (WBC) has been proposed to enhance the performance of write operations, the development of a unified WBC management scheme that is effective for diverse types of access patterns is still a challenging task. In this paper, a novel WBC management scheme named expectation-based least recently used (ExLRU) is proposed to improve the performance of flash memory through effectively reducing the number of erase operations and write activities. Different from the previous works, ExLRU accurately maintains access history information in the WBC, based on which a novel cost model is constructed to select data with the minimum write cost to write to flash memory. An efficient ExLRU implementation with negligible overhead is developed. Simulation results show that ExLRU outperforms state-of-the-art WBC management schemes under various workloads.

Research Area(s)

  • Block split, ExLRU-Clock, expectation-based least recently used (ExLRU), flash memory, write buffer cache (WBC)

Citation Format(s)

A unified write buffer cache management scheme for flash memory. / Shi, Liang; Li, Jianhua; Li, Qingan; Xue, Chun Jason; Yang, Chengmo; Zhou, Xuehai.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 12, 6705640, 12.2014, p. 2779-2792.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review