TY - GEN
T1 - A Theoretical Examination of the Circuit Requirements of Power Factor Correction
AU - Tse, C. K.
AU - Chow, M. H. L.
PY - 1998/5
Y1 - 1998/5
N2 - In the first part of the paper, the requirements of circuits containing linear inductors, capacitors and ideal switches for the synthesis of power-factor-correction (PFC) converters are examined. Sufficient conditions for achieving PFC are stated in terms of the circuit topology and the switching sequence. Various topologies, from the simplest buck, boost, and buck-boost converters to fourth-order Cuk, Zeta and SEPIC converters, are examined in the light of these topological conditions. In the second part of the paper, the general configuration of power supplies that provide PFC and voltage regulation will be discussed. It consists of two simple power stages forming a three-port network which is terminated to an input voltage, a storage capacitor and an output load. The various possible arrangements of the two constituent power stages will be discussed with emphasis on minimizing the amount of power that is processed serially by the power stages.
AB - In the first part of the paper, the requirements of circuits containing linear inductors, capacitors and ideal switches for the synthesis of power-factor-correction (PFC) converters are examined. Sufficient conditions for achieving PFC are stated in terms of the circuit topology and the switching sequence. Various topologies, from the simplest buck, boost, and buck-boost converters to fourth-order Cuk, Zeta and SEPIC converters, are examined in the light of these topological conditions. In the second part of the paper, the general configuration of power supplies that provide PFC and voltage regulation will be discussed. It consists of two simple power stages forming a three-port network which is terminated to an input voltage, a storage capacitor and an output load. The various possible arrangements of the two constituent power stages will be discussed with emphasis on minimizing the amount of power that is processed serially by the power stages.
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U2 - 10.1109/PESC.1998.703229
DO - 10.1109/PESC.1998.703229
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 0780344898
VL - 2
T3 - PESC Record - IEEE Annual Power Electronics Specialists Conference
SP - 1415
EP - 1421
BT - Proceedings of PESC Record - IEEE Annual Power Electronics Specialists Conference
T2 - Proceedings of the 1998 IEEE 29th Annual Power Electronics Specialists Conference, PESC. Part 2 (of 2)
Y2 - 18 May 1998 through 21 May 1998
ER -