A SYSTEM-ON-CHIP 1.5 GHz PHASE LOCKED LOOP REALIZED USING 40 nm CMOS TECHNOLOGY

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Detail(s)

Original languageEnglish
Pages (from-to)101-113
Journal / PublicationFacta universitatis - series: Electronics and Energetics
Volume31
Issue number1
Publication statusPublished - Mar 2018

Abstract

This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifier-feedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz.

Research Area(s)

  • PLL, blind zone, current mismatch, ring oscillator