@inproceedings{948b4a3f79fb4a17a638b92b1d8fd716,
title = "A system on chip design framework for prime number validation using reconfigurable hardware",
abstract = "This paper presents a System on Chip (SoC) design framework for prime number validation which targets reconfigurable hardware. The primality test is crucial for most security systems using public-key schemes. It has been recognised that strong prime number generation is important, and prime validation is an intrinsic part of the generation. Our main contributions include: (1) A design method for mapping the Rabin-Miller Pseudoprime Test into hardware. (2) Parallel designs for Montgomery modular arithmetic operations. (3) A design generator for producing hardware prime number validators based on user-defined parameters. (4) An implementation of the proposed architectures in reconfigurable devices, with an evaluation of its effectiveness compared with other methods. (5) A scalable framework for parallelizing prime validations in reconfigurable hardware. {\textcopyright} Springer-Verlag Berlin Heidelberg 2004",
author = "Cheung, \{Ray C. C.\}",
year = "2004",
doi = "10.1007/978-3-540-30117-2\_173",
language = "English",
isbn = "9783540229896",
series = "Lecture Notes in Computer Science",
publisher = "Springer ",
pages = "1186--1187",
editor = "Becker, \{J{\"u}rgen \} and Platzner, \{Marco \} and Vernalde, \{Serge \}",
booktitle = "Field Programmable Logic and Application",
note = "14th International Conference on Field Programmable Logic and Applications (FPL 2004) ; Conference date: 30-08-2004 Through 01-09-2004",
}