A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs

A novel phase-noise-filtering technique based on phase-domain averaging is proposed to suppress the large injection spurs and poor high-frequency phase noise of inductor-less injection-locked phase-locked loops (IL-PLLs). Demonstrated using a 1.2-GHz fractional-N IL-PLL based on a capacitive-ring-coupled ring oscillator, wideband spur-and-phase-noise suppression of up to 20 dB is achieved allowing for phase noise as low as -146 dBc/Hz at 30-MHz offset with a 2-MHz resolution. This allows for an inductor-less alternative to LC-based PLLs in scaled-digital CMOS technologies. The 65-nm CMOS prototype improves 10-MHz phase noise from -115 to -135 dBc/Hz, injection spurs from -40.5 to -57 dB, and integrated jitter from 3.57 to 1.48 ps while occupying an area of 0.6 mm2 and consuming 19.8 mW from a 0.85-V supply, resulting in an FoM and FoMJitter of -163 and -223.6 dB, respectively.