TY - GEN
T1 - A signal folding neural amplifier exploiting neural signal statistics
AU - Chen, Yi
AU - Basu, Arindam
AU - Je, Minkyu
N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].
PY - 2012
Y1 - 2012
N2 - A novel amplifier for neural recording applications that exploits the 1/n characteristics of neural signals is described in this paper. Comparison and reset circuits are implemented with the core amplifier to fold a large output waveform into a preset range enabling the use of an ADC with less number of bits for the same effective dynamic range. This also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. At the receiver, a reconstruction algorithm is applied in the digital domain to recover the amplified signal from the folded waveform. Other features of this proposed amplifier are increased reliability due to removal of pseudo-resistors, less distortion and low-voltage operation. Measurement results from a 65nm CMOS implementation of a prototype are presented. © 2012 IEEE.
AB - A novel amplifier for neural recording applications that exploits the 1/n characteristics of neural signals is described in this paper. Comparison and reset circuits are implemented with the core amplifier to fold a large output waveform into a preset range enabling the use of an ADC with less number of bits for the same effective dynamic range. This also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. At the receiver, a reconstruction algorithm is applied in the digital domain to recover the amplified signal from the folded waveform. Other features of this proposed amplifier are increased reliability due to removal of pseudo-resistors, less distortion and low-voltage operation. Measurement results from a 65nm CMOS implementation of a prototype are presented. © 2012 IEEE.
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U2 - 10.1109/BioCAS.2012.6418456
DO - 10.1109/BioCAS.2012.6418456
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781467322935
T3 - 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications
SP - 224
EP - 227
BT - 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications
T2 - 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012
Y2 - 28 November 2012 through 30 November 2012
ER -