Abstract
This paper presents a fully parallelized and scalable RNS Montgomery multiplier over binary field. By generalizing the RNS Montgomery Multiplication (RNS MM) and elaborating a highly efficient RNS base selection, we are able to obtain a considerably high speed in our FPGA implementation experiments with acceptable circuit area and modest critical path delay. Furthermore, this design can be easily scalable by adjusting a variety of field sizes and field polynomials. © IEICE 2013.
Original language | English |
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Journal | IEICE Electronics Express |
Volume | 10 |
Issue number | 23 |
DOIs | |
Publication status | Published - 10 Dec 2013 |
Research Keywords
- Binary field
- FPGA
- RNS MM
- Scalable