TY - GEN
T1 - A reconfigurable architecture for real-time prediction of neural activity
AU - Li, Will X. Y.
AU - Cheung, Ray C. C.
AU - Chan, Rosa H. M.
AU - Song, Dong
AU - Berger, Theodore W.
PY - 2013
Y1 - 2013
N2 - In this paper, we propose an FPGA-based hardware architecture for conducting real-time prediction of neural activity using a second-order generalized Laguerre-Volterra model (GLVM). This architecture serves as a rapid prototype of the prediction module of the future cognitive neural prosthetic device. We validate the functionality of the hardware model by utilizing the neuronal firing data of behaving rats trained to perform the delayed nonmatch-to-sample (DNMS) memory task. © 2013 IEEE.
AB - In this paper, we propose an FPGA-based hardware architecture for conducting real-time prediction of neural activity using a second-order generalized Laguerre-Volterra model (GLVM). This architecture serves as a rapid prototype of the prediction module of the future cognitive neural prosthetic device. We validate the functionality of the hardware model by utilizing the neuronal firing data of behaving rats trained to perform the delayed nonmatch-to-sample (DNMS) memory task. © 2013 IEEE.
UR - https://www.scopus.com/pages/publications/84883349732
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84883349732&origin=recordpage
U2 - 10.1109/ISCAS.2013.6572230
DO - 10.1109/ISCAS.2013.6572230
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781467357609
SP - 1869
EP - 1872
BT - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013)
Y2 - 19 May 2013 through 23 May 2013
ER -