A realizable architecture for genetic algorithm parallelism

A novel hardware architecture is specifically designed here to fulfil the realization of parallelism of genetic algorithms. It is a modular structure which consists of three individual processing units, namely the Genetic Operator, the Fitness Evaluator and the Objective Function Sequencer. Each unit is implemented by the use of an FPGA chip. Due to its modular structure, this design possesses a unique flexible and scalable feature that is capable of handling various engineering applications. Such a scalable feature can markedly improve the computing speed of this hardware simply by the increase in the fitness evaluators. The results obtained are very encouraging for future development, particularly where genetic algorithms are used in real-time system applications. © 1998 Published by Elsevier Science Ltd. All rights reserved.