A realizable architecture for genetic algorithm parallelism
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Pages (from-to) | 897-903 |
| Journal / Publication | Control Engineering Practice |
| Volume | 6 |
| Issue number | 7 |
| Publication status | Published - Jul 1998 |
Link(s)
Abstract
A novel hardware architecture is specifically designed here to fulfil the realization of parallelism of genetic algorithms. It is a modular structure which consists of three individual processing units, namely the Genetic Operator, the Fitness Evaluator and the Objective Function Sequencer. Each unit is implemented by the use of an FPGA chip. Due to its modular structure, this design possesses a unique flexible and scalable feature that is capable of handling various engineering applications. Such a scalable feature can markedly improve the computing speed of this hardware simply by the increase in the fitness evaluators. The results obtained are very encouraging for future development, particularly where genetic algorithms are used in real-time system applications. © 1998 Published by Elsevier Science Ltd. All rights reserved.
Research Area(s)
- Filter design, Genetic algorithms, Hardware architectures, Parallelism
Citation Format(s)
A realizable architecture for genetic algorithm parallelism. / Tang, K. S.; Man, K. F.; Ho, Y. C. et al.
In: Control Engineering Practice, Vol. 6, No. 7, 07.1998, p. 897-903.
In: Control Engineering Practice, Vol. 6, No. 7, 07.1998, p. 897-903.
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
