A queueing network model for semiconductor manufacturing

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Author(s)

Detail(s)

Original languageEnglish
Pages (from-to)412-427
Journal / PublicationIEEE Transactions on Semiconductor Manufacturing
Volume9
Issue number3
Publication statusPublished - 1996
Externally publishedYes

Abstract

We develop an open queueing network model for rapid performance analysis of semiconductor manufacturing facilities. While the use of queueing models for performance evaluation of manufacturing systems is not new, our approach differs from others in the detailed ways in which we model the different tool groups found in semiconductor wafer fabrication, as well as the way in which we characterize the effect of rework and scrap on wafer lot sizes. As an application of the model, we describe a method for performing tool planning for semiconductor lines. The method is based on a marginal allocation procedure which uses performance estimates from the queueing network model to determine the number of tools needed to achieve a target cycle time, with the objective being to minimize overall equipment cost. © 1996 IEEE.

Citation Format(s)

A queueing network model for semiconductor manufacturing. / Connors, Daniel P.; Feigin, Gerald E.; Yao, David D.

In: IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 3, 1996, p. 412-427.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review