A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices

Emerging non-memory technologies have been widely employed in intermittently powered IoT devices to bridge program execution across different power cycles. Together with register contents, the cache contents will be checkpointed to non-volatile memory upon power outages. While pure nonvolatile memory-based cache is an intuitive option, it suffers from inferior performance due to high write latency and energy overhead. We introduce a STT-RAM-based hybrid cache which is specifically tailored for the intermittently-powered embedded system. This cache design supports both normal memory access and checkpointing: during normal access, the large density of STT-RAM and fast access speed of SRAM are fully taken advantage to achieve high performance and low energy consumption; during checkpointing, the most important cache blocks in SRAM are migrated to the dead or unimportant clean cache blocks in STT-RAM. The experimental results demonstrate a 1.3× execution progress improvement compared with pure non-volatile cache design.