A management strategy for the reliability and performance improvement of MLC-based flash-memory storage systems

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

24 Scopus Citations
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Author(s)

Detail(s)

Original languageEnglish
Article number5483292
Pages (from-to)305-320
Journal / PublicationIEEE Transactions on Computers
Volume60
Issue number3
Online published7 Jun 2010
Publication statusPublished - Mar 2011
Externally publishedYes

Abstract

Cost has been a major driving force in the development of the flash-memory technology. Because of this, serious challenges are now faced for future products on reliability and performance requirements. In this work, we propose a management strategy to resolve the reliability and performance problems of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of advanced multilevel cell flash-memory chips. The capability of the proposed approach is analyzed with reliability considerations and evaluated by experiments over realistic workloads with respect to the reliability and performance improvement.

Research Area(s)

  • address translation, disposable flash memory, Flash-memory management software, MLC flash memory, performance enhancement, reliability enhancement, update commitment