A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks

Govind Narasimman; Subhrajit Roy; Xuanyao Fong; Kaushik Roy; Chip-Hong Chang; Arindam Basu

doi:10.1109/ISCAS.2016.7527390

A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks

Govind Narasimman
, Subhrajit Roy
, Xuanyao Fong
, Kaushik Roy
, Chip-Hong Chang
, Arindam Basu^*

^*Corresponding author for this work

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

8 Citations (Scopus)

Abstract

Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However, these approaches require high voltages (≈ 3-12V) for weight update and entail high energy for learning (≈ 4-30pJ/write). We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈ 40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Pages	914-917
Volume	2016-July
ISBN (Print)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527390
Publication status	Published - 29 Jul 2016
Externally published	Yes
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 22 May 2016 → 25 May 2016

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Conference

Conference	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Place	Canada
City	Montreal
Period	22/05/16 → 25/05/16

Bibliographical note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

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Narasimman, G., Roy, S., Fong, X., Roy, K., Chang, C.-H., & Basu, A. (2016). A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (Vol. 2016-July, pp. 914-917). Article 7527390 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). IEEE. https://doi.org/10.1109/ISCAS.2016.7527390

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title = "A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks",

abstract = "Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However, these approaches require high voltages (≈ 3-12V) for weight update and entail high energy for learning (≈ 4-30pJ/write). We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈ 40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset.",

author = "Govind Narasimman and Subhrajit Roy and Xuanyao Fong and Kaushik Roy and Chip-Hong Chang and Arindam Basu",

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Narasimman, G, Roy, S, Fong, X, Roy, K, Chang, C-H & Basu, A 2016, A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems. vol. 2016-July, 7527390, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, IEEE, pp. 914-917, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 22/05/16. https://doi.org/10.1109/ISCAS.2016.7527390

A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. / Narasimman, Govind; Roy, Subhrajit; Fong, Xuanyao et al.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July IEEE, 2016. p. 914-917 7527390 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

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AU - Roy, Subhrajit

AU - Fong, Xuanyao

AU - Roy, Kaushik

AU - Chang, Chip-Hong

AU - Basu, Arindam

N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

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Y1 - 2016/7/29

N2 - Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However, these approaches require high voltages (≈ 3-12V) for weight update and entail high energy for learning (≈ 4-30pJ/write). We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈ 40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset.

AB - Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However, these approaches require high voltages (≈ 3-12V) for weight update and entail high energy for learning (≈ 4-30pJ/write). We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈ 40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset.

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PB - IEEE

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ER -

Narasimman G, Roy S, Fong X, Roy K, Chang CH, Basu A. A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July. IEEE. 2016. p. 914-917. 7527390. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2016.7527390

A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks

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