A Low-Voltage Folded-Switching Mixer Using Area-Efficient CCG Transconductor

This brief presents a low-voltage folded-switching mixer in 65-nm CMOS process. A modified complimentary common gate pair is utilized as the input transconductance stage, where a transformer is subtly applied for chip size reduction. Benefitted from the current reuse, the pMOS transistor not only works for radio frequency (RF) signal amplification, but also acts as the current bleeding path. This improves the conversion gain (CG), benefits the noise figure, and merits the mixer applicable in low-supply voltage. An inductive peaking scheme is also employed to further improve the CG and broaden the gain bandwidth. The presented mixer works under a low-supply voltage of 1 V and occupies an active area of only 0.24 mm². Measured results exhibit the CG of 10.5 dB with 3-dB bandwidth ranging from 4 to 8.8 GHz, double-sideband noise figure from 3.8 to 5.2 dB, input return loss lower than -8.1 dB, and LO-to-RF isolation better than 46 dB.