A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

Qian ZHOU; Yan HAN; Shifeng ZHANG; Xiaoxia HAN; Lu JIE; Ray C. C. CHEUNG; Guangtao FENG

doi:10.1007/s11432-016-0301-3

A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

Qian ZHOU, Yan HAN^*, Shifeng ZHANG, Xiaoxia HAN, Lu JIE, Ray C. C. CHEUNG, Guangtao FENG

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

1 Citation (Scopus)

Original language	English
Article number	089401
Journal	Science China Information Sciences
Volume	60
Issue number	8
Online published	20 Jan 2017
DOIs	https://doi.org/10.1007/s11432-016-0301-3
Publication status	Published - Aug 2017

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@article{5da7b3d5ee894e05b5700a868fe53276,

title = "A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process",

author = "Qian ZHOU and Yan HAN and Shifeng ZHANG and Xiaoxia HAN and Lu JIE and CHEUNG, {Ray C. C.} and Guangtao FENG",

year = "2017",

month = aug,

doi = "10.1007/s11432-016-0301-3",

language = "English",

volume = "60",

journal = "Science China Information Sciences",

issn = "1674-733X",

publisher = "Springer Nature and Science China Press",

number = "8",

}

TY - JOUR

T1 - A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

AU - ZHOU, Qian

AU - HAN, Yan

AU - ZHANG, Shifeng

AU - HAN, Xiaoxia

AU - JIE, Lu

AU - CHEUNG, Ray C. C.

AU - FENG, Guangtao

PY - 2017/8

Y1 - 2017/8

UR - http://www.scopus.com/inward/record.url?scp=85010773830&partnerID=8YFLogxK

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-85010773830&origin=recordpage

U2 - 10.1007/s11432-016-0301-3

DO - 10.1007/s11432-016-0301-3

M3 - RGC 21 - Publication in refereed journal

SN - 1674-733X

VL - 60

JO - Science China Information Sciences

JF - Science China Information Sciences

IS - 8

M1 - 089401

ER -

A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

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