Abstract
This paper presents a low-power high-resolution band-pass ΣΔ ADC for accelerometer applications. The proposed band-pass ΣΔ ADC consists of a high-performance 6-th order feed-forward ΣΔ modulator with 1-bit quantization and a low-power, area-efficient digital filter. The ADC is fabricated in 180 nm 1P6M mixed-signal CMOS process with a die area of 5 mm2. This high-resolution ADC got 90 dB peak signal to noise plus distortion ratio (SNDR) and 96 dB dynamic range (DR) over 4 kHz bandwidth, while the intermediate frequency (IF) is shifting from 100 KHz to 200 KHz. The power dissipation of the chip is 5.6 mW under 1.8 V (digital)/3.3 V (analog) power supply.
| Original language | English |
|---|---|
| Pages (from-to) | 438-445 |
| Journal | Journal of Semiconductor Technology and Science |
| Volume | 17 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - Jun 2017 |
Research Keywords
- Accelerometer
- Band pass
- High-resolution
- Low-power
- ΣΔ ADC
Fingerprint
Dive into the research topics of 'A low-power high-resolution band-pass sigma-delta ADC for accelerometer applications'. Together they form a unique fingerprint.Cite this
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver