A low phase noise V-band 40 NM CMOS phase locked loop for wireless communication
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
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Detail(s)
Original language | English |
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Pages (from-to) | 278-283 |
Journal / Publication | Microwave and Optical Technology Letters |
Volume | 59 |
Issue number | 2 |
Publication status | Published - 1 Feb 2017 |
Link(s)
Abstract
This letter presents a V-band phase-locked loop (PLL) that employs mutual injection-locking voltage controlled oscillator (VCO) and zero blind zone phase frequency detector (PFD) to enhance phase noise performance. This architecture is physically implemented in 40nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an in-band phase noise of −90dBc/Hz at 500 kHz offset and −92dBc/Hz at 1MHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:278–283, 2017.
Research Area(s)
- low phase noise, mutual injection locking, V-band PLL
Citation Format(s)
A low phase noise V-band 40 NM CMOS phase locked loop for wireless communication. / Zhou, Qian; Han, Yan; Zhang, Shifeng et al.
In: Microwave and Optical Technology Letters, Vol. 59, No. 2, 01.02.2017, p. 278-283.Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review