A low phase noise V-band 40 NM CMOS phase locked loop for wireless communication

This letter presents a V-band phase-locked loop (PLL) that employs mutual injection-locking voltage controlled oscillator (VCO) and zero blind zone phase frequency detector (PFD) to enhance phase noise performance. This architecture is physically implemented in 40nm CMOS process with a die area of 0.7 mm². The silicon results demonstrate an in-band phase noise of −90dBc/Hz at 500 kHz offset and −92dBc/Hz at 1MHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:278–283, 2017.