A high-performance, low-power σ Δ ADC for digital audio applications
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Pages (from-to) | 0550091-0550097 |
| Journal / Publication | Journal of Semiconductors |
| Volume | 31 |
| Issue number | 5 |
| Publication status | Published - 2010 |
Link(s)
Abstract
A high-performance low-power σ Δ analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded σ Δ modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm 2, which dissipates only 2.1 mA quiescent current in the analog circuits. © 2010 Chinese Institute of Electronics.
Research Area(s)
- σ δ modulator, Audio analog-to-digital converter, Decimation filter, Low power
Citation Format(s)
A high-performance, low-power σ Δ ADC for digital audio applications. / Hao, Luo; Yan, Han; Cheung, Ray C. C. et al.
In: Journal of Semiconductors, Vol. 31, No. 5, 2010, p. 0550091-0550097.Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
