A hardware-accelerated solution for hierarchical index-based merge-join (Extended Abstract)
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
Original language | English |
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Title of host publication | Proceedings - 2019 IEEE 35th International Conference on Data Engineering |
Subtitle of host publication | ICDE 2019 |
Publisher | Institute of Electrical and Electronics Engineers, Inc. |
Pages | 2137-2138 |
ISBN (electronic) | 9781538674741 |
ISBN (print) | 9781538674758 |
Publication status | Published - Apr 2019 |
Publication series
Name | Proceedings - International Conference on Data Engineering |
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Volume | 2019-April |
ISSN (Print) | 1063-6382 |
ISSN (electronic) | 2375-026X |
Conference
Title | 35th IEEE International Conference on Data Engineering (ICDE 2019) |
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Location | Parisian Macao |
Place | Macao |
Period | 8 - 11 April 2019 |
Link(s)
Abstract
Hardware acceleration through field programmable gate arrays (FPGAs) has recently become a technique of growing interest for many data-intensive applications. Join query is one of the most fundamental database query types useful in relational database management systems. However, the available solutions so far have been beset by higher costs in comparison with other query types. In this paper, we develop a novel solution to accelerate the processing of sort-merge join queries with low match rates. Specifically, our solution makes use of hierarchical indexes to identify result-yielding regions in the solution space in order to take advantage of result sparseness. Further, in addition to one-dimensional equi-join query processing, our solution supports processing of multidimensional similarity join queries. Experimental results show that our solution is superior to the best existing method in a low match rate setting; the method achieves a speedup factor of 4.8 for join queries with a match rate of 5%.
Research Area(s)
- B+tree, FPGA, Hardware acceleration, Low selectivity join, Sort merge join
Citation Format(s)
A hardware-accelerated solution for hierarchical index-based merge-join (Extended Abstract). / Zhou, Zimeng; Yu, Chenyun; Nutanong, Sarana et al.
Proceedings - 2019 IEEE 35th International Conference on Data Engineering: ICDE 2019. Institute of Electrical and Electronics Engineers, Inc., 2019. p. 2137-2138 8731391 (Proceedings - International Conference on Data Engineering; Vol. 2019-April).
Proceedings - 2019 IEEE 35th International Conference on Data Engineering: ICDE 2019. Institute of Electrical and Electronics Engineers, Inc., 2019. p. 2137-2138 8731391 (Proceedings - International Conference on Data Engineering; Vol. 2019-April).
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review