A Hardware Gaussian Noise Generator Using the Wallace Method

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Author(s)

Detail(s)

Original languageEnglish
Pages (from-to)911-920
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume13
Issue number8
Publication statusPublished - Aug 2005
Externally publishedYes

Abstract

We describe a hardware Gaussian noise generator based on the Wallace method used for a hardware simulation system. Our noise generator accurately models a true Gaussian probability density function even at high σ values. We evaluate its properties using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test and 2) an application for decoding of low-density parity-check (LDPC) codes. Our design is implemented on a Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) at 155 MHz; it takes up 3% of the device and produces 155 million samples per second, which is three times faster than a 2.6-GHz Pentium-IV PC. Another implementation on a Xilinx Spartan-III XC3S200E-5 FPGA at 106 MHz is two times faster than the software version. Further improvement in performance can be obtained by concurrent execution: 20 parallel instances of the noise generator on an XC2V4000-6 FPGA at 115 MHz can run 51 times faster than software on a 2.6-GHz Pentium-IV PC. © 2005 IEEE.

Research Area(s)

  • Channel coding, Communication channels, Field-programmable gate arrays (FPGAs), Gaussian noise, High-performance, Monte Carlo methods, Reconfigurable- computing, Technology-mapping

Citation Format(s)

A Hardware Gaussian Noise Generator Using the Wallace Method. / Lee, Dong-U; Luk, Wayne; Villasenor, John D.; Zhang, Guanglie; Leong, Philip H.W.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 8, 08.2005, p. 911-920.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review