A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC

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Original languageEnglish
Article number7517220
Pages (from-to)2702-2713
Journal / PublicationIEEE Transactions on Circuits and Systems for Video Technology
Issue number12
Online published20 Jul 2016
Publication statusPublished - Dec 2017


Ultrahigh definition (UHD), such as 4K/8K, is becoming the mainstream of video resolution nowadays. High Efficiency Video Coding (HEVC) is the emerging video coding standard to process the encoding and decoding of UHD video. This paper first develops multiple techniques that allow the proposed hardware architecture for intra prediction of HEVC working in full pipeline. The proposed techniques include: 1) a novel buffer structure for reference samples; 2) a mode-dependent scanning order; and 3) an inverse method for reference sample extension. The size of the buffer is 3K b for luma component and 3K b for chroma components, providing sufficient accessing to the reference samples. Since the data dependency between two neighboring blocks is addressed by the mode-dependent scanning order, the proposed fully pipelined design can produce 4 pixels/clock cycle. As a result, the throughput of the proposed architecture is capable to support 3840 × 2160 videos at 30 frames/s.

Research Area(s)

  • Field-programmable gate array (FPGA), hardware architecture, HEVC, intra prediction