A fully integrated architecture for fast programming of floating gates

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Original languageEnglish
Article number4252795
Pages (from-to)957-960
Journal / PublicationProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2007
Externally publishedYes


Title2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
PlaceUnited States
CityNew Orleans, LA
Period27 - 30 May 2007


We present an on-chip system that enables programming floating gate arrays at a high speed. The main component allowing this speedup is a floating point current measuring ADC operating over 4 decades at 10bit accuracy or 7decades at 7 bit accuracy. The conversion time is around 200 μs till around 30 pA of current. The gate and drain voltages are set by on-chip DACs. The digital words for the DAC are sent by an FPGA through an SPI interface. The controller for sequencing the operations as well as the look-up-table with characterization data are on the FPGA. Algorithms using either pulse-width modulation or drain voltage modulation can be implemented. © 2007 IEEE.

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