A fully integrated architecture for fast and accurate programming of floating gates over six decades of current
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review
Author(s)
Detail(s)
Original language | English |
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Article number | 5437216 |
Pages (from-to) | 953-962 |
Journal / Publication | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 19 |
Issue number | 6 |
Publication status | Published - Jun 2011 |
Externally published | Yes |
Link(s)
Abstract
This paper presents an on-chip system with digital serial peripheral interface (SPI) interface that enables accurate programming of floating gate arrays at a high speed. The main component allowing this speedup is a floating point current measuring analog-to-digital convertor (ADC). The ADC comprises a wide range logarithmic transimpedance amplifier (TIA) followed by a linear ramp ADC. The TIA operates over seven decades of current going down to sub-pA levels. It incorporates an adaptive biasing scheme to save power. The topology provides a relatively temperature independent measurement of the floating-gate voltage. The TIA-ADC combination operates over six decades at a thermal noise limited accuracy of 9.5 bits when average conversion time is around 500 μs. The system features level-shifters and selection circuitry at the periphery of the floating gate array, current-steering digital-to-analog converters (DACs) to set gate and drain voltages, and SPI for a microprocessor or field-programmable gate array (FPGA). Algorithms using either pulse-width modulation or drain voltage modulation can be implemented on this platform. We present data for this system from 0.5 μm AMI and 0.35 μ m TSMC processes. © 2010 IEEE.
Research Area(s)
- Floating-gate programming, floating-point analog-to-digital converter (ADC), hot-electron injection, logarithmic compression, low power, programmable analog
Bibliographic Note
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Citation Format(s)
A fully integrated architecture for fast and accurate programming of floating gates over six decades of current. / Basu, Arindam; Hasler, Paul E.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 6, 5437216, 06.2011, p. 953-962.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 6, 5437216, 06.2011, p. 953-962.
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review