A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

5 Scopus Citations
View graph of relations

Author(s)

Detail(s)

Original languageEnglish
Pages (from-to)499-501
Journal / PublicationIEEE Communications Letters
Volume7
Issue number10
Publication statusPublished - Oct 2003
Externally publishedYes

Abstract

We present a framework for solving logical topology design (LTD) problems in a constrained amount of computation time. Our framework uses a search space dimensionality (SSD) reduction technique that exploits a tradeoff between computation time and solution quality. We have demonstrated that our framework offers improved solution quality in comparison to an existing SSD reduction technique reported in the literature.

Research Area(s)

  • Logical topology design, Mixed integer linear programming, Optical networks, Routing