A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time

Andrew Zalesky; Hai Le Vu; Moshe Zukerman; Iradj Ouveysi

doi:10.1109/LCOMM.2003.818883

Author(s)

Andrew Zalesky
Hai Le Vu
Moshe Zukerman
Iradj Ouveysi

Detail(s)

Original language	English
Pages (from-to)	499-501
Journal / Publication	IEEE Communications Letters
Volume	7
Issue number	10
Publication status	Published - Oct 2003
Externally published	Yes

Link(s)

DOI	DOI https://doi.org/10.1109/LCOMM.2003.818883 Final Published version
	Check@CityULib
Link to Scopus	https://www.scopus.com/record/display.uri?eid=2-s2.0-0242332740&origin=recordpage
Permanent Link	https://scholars.cityu.edu.hk/en/publications/publication(6964835f-07db-4a42-8b86-009510781951).html

Abstract

We present a framework for solving logical topology design (LTD) problems in a constrained amount of computation time. Our framework uses a search space dimensionality (SSD) reduction technique that exploits a tradeoff between computation time and solution quality. We have demonstrated that our framework offers improved solution quality in comparison to an existing SSD reduction technique reported in the literature.

Research Area(s)

Logical topology design, Mixed integer linear programming, Optical networks, Routing

Citation Format(s)

[ RIS ] [ BibTeX ]

A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time. / Zalesky, Andrew; Vu, Hai Le; Zukerman, Moshe et al.
In: IEEE Communications Letters, Vol. 7, No. 10, 10.2003, p. 499-501.

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

Zalesky, A, Vu, HL, Zukerman, M & Ouveysi, I 2003, 'A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time', IEEE Communications Letters, vol. 7, no. 10, pp. 499-501. https://doi.org/10.1109/LCOMM.2003.818883

Zalesky, A., Vu, H. L., Zukerman, M., & Ouveysi, I. (2003). A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time. IEEE Communications Letters, 7(10), 499-501. https://doi.org/10.1109/LCOMM.2003.818883

Zalesky A, Vu HL, Zukerman M, Ouveysi I. A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time. IEEE Communications Letters. 2003 Oct;7(10):499-501. doi: 10.1109/LCOMM.2003.818883

Zalesky, Andrew ; Vu, Hai Le ; Zukerman, Moshe et al. / A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time. In: IEEE Communications Letters. 2003 ; Vol. 7, No. 10. pp. 499-501.