A flexible and customizable architecture for the relaxation labeling algorithm

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

2 Scopus Citations
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Detail(s)

Original languageEnglish
Article number6476651
Pages (from-to)106-110
Journal / PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
Volume60
Issue number2
Publication statusPublished - Feb 2013

Abstract

This brief presents a flexible and customizable architecture for the probabilistic relaxation labeling (PRL) algorithm. The algorithm has been restructured by using a hardware-friendly process that is executed on the proposed architecture. This enables the design to handle different numbers of objects and labels flexibly. Moreover, in the design, the proposed PRL unit can be easily duplicated for K times according to the available resources on the field-programmable gate array (FPGA). In this brief, K can be scalable up to 10 by using a Virtex-6 FPGA XC6VLX240T platform. Compared with existing architectures that are not suitable for a large number of objects, the proposed architecture reduces the time complexity from O(N × M) to O(N) with the same O(N × M2) space complexity, where N and M are the numbers of objects and labels, respectively. The experimental results show that the execution time of our design is about 15 times less for five objects and about 35 times less for a 128 × 64 image block than the software implementation running on a Quad-core Intel 32-nm machine. © 2013 IEEE.

Research Area(s)

  • Field-programmable gate array (FPGA), Parallel architecture, Relaxation labeling algorithm