TY - GEN
T1 - A digitally assisted, pseudo-resistor-less amplifier in 65nm CMOS for neural recording applications
AU - Chen, Yi
AU - Basu, Arindam
AU - Je, Minkyu
N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].
PY - 2012
Y1 - 2012
N2 - A novel scheme for amplification in neural recording systems is proposed in this work that allows us to remove the large 'pseudo-resistors' needed to bias the typically used capacitive amplifier topology. Comparison and reset circuits are implemented with the core amplifier to fold the output waveform of amplifier into a preset range for digitizing by an ADC. A reconstruction algorithm is then used in the digital domain to recover the amplified signal from the folded waveform. By removing the pseudo-resistors, higher robustness, less noise in LFP band and better matching and programmability of high pass corner can be achieved in the proposed design. Simulation and measurement results are presented from a prototype fabricated in 65nm CMOS. The presented scheme is general and can be used with any capacitive amplifier. © 2012 IEEE.
AB - A novel scheme for amplification in neural recording systems is proposed in this work that allows us to remove the large 'pseudo-resistors' needed to bias the typically used capacitive amplifier topology. Comparison and reset circuits are implemented with the core amplifier to fold the output waveform of amplifier into a preset range for digitizing by an ADC. A reconstruction algorithm is then used in the digital domain to recover the amplified signal from the folded waveform. By removing the pseudo-resistors, higher robustness, less noise in LFP band and better matching and programmability of high pass corner can be achieved in the proposed design. Simulation and measurement results are presented from a prototype fabricated in 65nm CMOS. The presented scheme is general and can be used with any capacitive amplifier. © 2012 IEEE.
UR - https://www.scopus.com/pages/publications/84867313183
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84867313183&origin=recordpage
U2 - 10.1109/MWSCAS.2012.6292033
DO - 10.1109/MWSCAS.2012.6292033
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781467325264
T3 - Midwest Symposium on Circuits and Systems
SP - 366
EP - 369
BT - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
T2 - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Y2 - 5 August 2012 through 8 August 2012
ER -