TY - GEN
T1 - A current-mode spiking neural classifier with lumped dendritic nonlinearity
AU - Banerjee, Amitava
AU - Kar, Sougata
AU - Roy, Subhrajit
AU - Bhaduri, Aritra
AU - Basu, Arindam
N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].
PY - 2015/7/27
Y1 - 2015/7/27
N2 - We present the current mode implementation of a spiking neural classifier with lumped square law dendritic nonlinearity. It has been shown earlier that such a system with binary synapses can be trained with structural plasticity algorithms to achieve comparable classification accuracy with less synaptic resources than conventional algorithms. Hence, in our address event based implementation, we save 2-12X memory resources in storing connectivity information. The chip fabricated in 0.35μm CMOS has 8 dendrites per cell and uses two opposing cells per class to cancel common mode inputs. Preliminary results show the chip is functional and dissipates 30nW of static power per neuronal cell and 422pJ/spike.
AB - We present the current mode implementation of a spiking neural classifier with lumped square law dendritic nonlinearity. It has been shown earlier that such a system with binary synapses can be trained with structural plasticity algorithms to achieve comparable classification accuracy with less synaptic resources than conventional algorithms. Hence, in our address event based implementation, we save 2-12X memory resources in storing connectivity information. The chip fabricated in 0.35μm CMOS has 8 dendrites per cell and uses two opposing cells per class to cancel common mode inputs. Preliminary results show the chip is functional and dissipates 30nW of static power per neuronal cell and 422pJ/spike.
UR - https://www.scopus.com/pages/publications/84946218436
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84946218436&origin=recordpage
U2 - 10.1109/ISCAS.2015.7168733
DO - 10.1109/ISCAS.2015.7168733
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781479983919
VL - 2015-July
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 714
EP - 717
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - IEEE
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -