A complementary architecture for high-speed true random number generator

Xian Yang; Ray C.C. Cheung

doi:10.1109/FPT.2014.7082786

A complementary architecture for high-speed true random number generator

Xian Yang
, Ray C.C. Cheung

Department of Electrical Engineering

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

13 Citations (Scopus)

Abstract

In this paper, we introduce a novel FPGA-based design for true random number generator (TRNG). It is able to harvest the timing difference caused by the nonuniformity of the Integrated Circuits (ICs) and use it to generate the randomness. Compared with the previous related work, this design uses a complementary scheme that leads to a doubled data rated output. The proposed complementary design has improved entropy and achieved higher throughput. The prototype design has been implemented and verified on a Xilinx Virtex-6 ML605 evaluation board. As a result, the generated random number stream is able to pass the statistical NIST and DIEHARD test suites showing a reliable performance. Meanwhile, it can approach the maximum data rate as 50 Mbps stably.

Original language	English
Title of host publication	Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014
Publisher	IEEE
Pages	248-251
ISBN (Print)	9781479962457
DOIs	https://doi.org/10.1109/FPT.2014.7082786
Publication status	Published - 8 Apr 2015
Event	13th International Conference on Field-Programmable Technology, FPT 2014 - Shanghai, China Duration: 10 Dec 2014 → 12 Dec 2014

Conference

Conference	13th International Conference on Field-Programmable Technology, FPT 2014
Place	China
City	Shanghai
Period	10/12/14 → 12/12/14

Access Output

10.1109/FPT.2014.7082786

Other Access Options

Check CityUHK Library

Permanent Link

Right click to copy link

Cite this

@inproceedings{93958dc8a35c4ff58e7000e717560894,

title = "A complementary architecture for high-speed true random number generator",

abstract = "In this paper, we introduce a novel FPGA-based design for true random number generator (TRNG). It is able to harvest the timing difference caused by the nonuniformity of the Integrated Circuits (ICs) and use it to generate the randomness. Compared with the previous related work, this design uses a complementary scheme that leads to a doubled data rated output. The proposed complementary design has improved entropy and achieved higher throughput. The prototype design has been implemented and verified on a Xilinx Virtex-6 ML605 evaluation board. As a result, the generated random number stream is able to pass the statistical NIST and DIEHARD test suites showing a reliable performance. Meanwhile, it can approach the maximum data rate as 50 Mbps stably.",

author = "Xian Yang and Cheung, \{Ray C.C.\}",

year = "2015",

month = apr,

day = "8",

doi = "10.1109/FPT.2014.7082786",

language = "English",

isbn = "9781479962457",

pages = "248--251",

booktitle = "Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014",

publisher = "IEEE",

address = "United States",

note = "13th International Conference on Field-Programmable Technology, FPT 2014 ; Conference date: 10-12-2014 Through 12-12-2014",

}

A complementary architecture for high-speed true random number generator. / Yang, Xian; Cheung, Ray C.C.
Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. IEEE, 2015. p. 248-251 7082786.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - A complementary architecture for high-speed true random number generator

AU - Yang, Xian

AU - Cheung, Ray C.C.

PY - 2015/4/8

Y1 - 2015/4/8

N2 - In this paper, we introduce a novel FPGA-based design for true random number generator (TRNG). It is able to harvest the timing difference caused by the nonuniformity of the Integrated Circuits (ICs) and use it to generate the randomness. Compared with the previous related work, this design uses a complementary scheme that leads to a doubled data rated output. The proposed complementary design has improved entropy and achieved higher throughput. The prototype design has been implemented and verified on a Xilinx Virtex-6 ML605 evaluation board. As a result, the generated random number stream is able to pass the statistical NIST and DIEHARD test suites showing a reliable performance. Meanwhile, it can approach the maximum data rate as 50 Mbps stably.

AB - In this paper, we introduce a novel FPGA-based design for true random number generator (TRNG). It is able to harvest the timing difference caused by the nonuniformity of the Integrated Circuits (ICs) and use it to generate the randomness. Compared with the previous related work, this design uses a complementary scheme that leads to a doubled data rated output. The proposed complementary design has improved entropy and achieved higher throughput. The prototype design has been implemented and verified on a Xilinx Virtex-6 ML605 evaluation board. As a result, the generated random number stream is able to pass the statistical NIST and DIEHARD test suites showing a reliable performance. Meanwhile, it can approach the maximum data rate as 50 Mbps stably.

UR - https://www.scopus.com/pages/publications/84928713829

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84928713829&origin=recordpage

U2 - 10.1109/FPT.2014.7082786

DO - 10.1109/FPT.2014.7082786

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9781479962457

SP - 248

EP - 251

BT - Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014

PB - IEEE

T2 - 13th International Conference on Field-Programmable Technology, FPT 2014

Y2 - 10 December 2014 through 12 December 2014

ER -

A complementary architecture for high-speed true random number generator

Abstract

Conference

Access Output

Other Access Options

Permanent Link

Other Files and Links

Fingerprint

Cite this